FIG. 5 is a block diagram to show the schematic configuration of a memory control unit for controlling SDRAM in a related art. In the figure, a memory control unit 100 is configured by a setting section 101 for retaining setup information to switch operation setting of SDRAM 200, a setting change detection section 102 for detecting a command signal from a bus master 300 indicating change of the setup information retained in the setting section 101, and a setting control section 103 for changing the setup information retained in the setting section 101 in accordance with the command signal detected by the setting change detection section 102. The memory control unit 100 generally is connected to a plurality of bus masters 300 and makes optimum operation setting for each bus master (for example, refer to patent document 1). Patent document 1: Japanese Patent Laid-Open No. 53252/1999